A power supply voltage is required to be above a certain threshold voltage to effectively operate an associated electronic circuit. When the power supply voltage falls below this threshold, for instance, after a power down condition such as removal or interruption of a power supply, a power down reset (PDR”) signal is asserted. The reset signal will hold the associated circuit in a reset state until the power supply voltage returns to a voltage level above a certain threshold voltage for effective circuit operation. If the-circuit is not in the reset state when the power supply voltage is below the operating threshold, the circuit may not operate properly.
Power down detection circuits may be used in different applications, including but not limited to cell phones and hard disk drives.
Much of the prior art focuses on power-up reset signals, where a reset signal is asserted when a power up condition is detected. In addition, the prior art relies on VDD to supply a voltage detector. This approach has come drawbacks, since it may be desirable to set different trip points which cannot be done if VDD supplies the voltage detector.
Therefore, it is desirable to have an improved circuit which will accurately detect a power down condition.